@article{DBLP:journals/tcad/KedemW84,
author = {Gershon Kedem and
Hiroyuki Watanabe},
title = {Graph-Optimization Techniques for IC Layout and Compaction},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {3},
number = {1},
year = {1984},
pages = {12-20},
ee = {http://dx.doi.org/10.1109/TCAD.1984.1270052},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Last update 2009-06-10 CET by the DBLP Team — 
Data released under the ODC-BY 1.0 license — See also our legal information page
