BibTeX
@article{DBLP:journals/tcad/KedemW84,
author = {Gershon Kedem and
Hiroyuki Watanabe},
title = {Graph-Optimization Techniques for IC Layout and Compaction},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {3},
number = {1},
year = {1984},
pages = {12-20},
ee = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28427{\&}arnumber=1270052{\&}count=14{\&}index=2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2006-07-25 by Michael Ley (ley@uni-trier.de)