Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.

Chandan Karfa Dipankar Sarkar Chitta Mandal Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. 479-492 2010 29 IEEE Trans. on CAD of Integrated Circuits and Systems 3 http://dx.doi.org/10.1109/TCAD.2009.2035542 db/journals/tcad/tcad29.html#KarfaSM10