A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.

Wen-Ben Jone Christos A. Papachristou A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. 374-384 1995 14 IEEE Trans. on CAD of Integrated Circuits and Systems 3 http://doi.ieeecomputersociety.org/10.1109/43.365128 db/journals/tcad/tcad14.html#JoneP95