A discrete syntax for level-sensitive latched circuits having n clocks and m phases.

Glenn Jennings Esther Jennings A discrete syntax for level-sensitive latched circuits having n clocks and m phases. 111-126 1996 15 IEEE Trans. on CAD of Integrated Circuits and Systems 1 http://doi.ieeecomputersociety.org/10.1109/43.486277 db/journals/tcad/tcad15.html#JenningsJ96