Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.

Himanshu Jain Daniel Kroening Natasha Sharygina Edmund M. Clarke Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. 366-379 2008 27 IEEE Trans. on CAD of Integrated Circuits and Systems 2 http://dx.doi.org/10.1109/TCAD.2007.907270 db/journals/tcad/tcad27.html#JainKSC08