Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.

Yu Hu Victor Shih Rupak Majumdar Lei He Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. 1751-1760 2008 27 IEEE Trans. on CAD of Integrated Circuits and Systems 10 http://dx.doi.org/10.1109/TCAD.2008.2003272 db/journals/tcad/tcad27.html#HuSMH08