Indradeep Ghosh Niraj K. Jha Sudipta Bhawmik A BIST scheme for RTL circuits based on symbolic testabilityanalysis. 111-128 2000 19 IEEE Trans. on CAD of Integrated Circuits and Systems 1 http://doi.ieeecomputersociety.org/10.1109/43.822624 db/journals/tcad/tcad19.html#GhoshJB00