Parity-scan design to reduce the cost of test application.

Hideo Fujiwara Akihiro Yamamoto Parity-scan design to reduce the cost of test application. 1604-1611 1993 12 IEEE Trans. on CAD of Integrated Circuits and Systems 10 http://doi.ieeecomputersociety.org/10.1109/43.256936 db/journals/tcad/tcad12.html#FujiwaraY93