<?xml version="1.0"?>
<dblp>
<article key="journals/tcad/BurchCLMD94" mdate="2006-05-31">
<author>Jerry R. Burch</author>
<author>Edmund M. Clarke</author>
<author>David E. Long</author>
<author>Kenneth L. McMillan</author>
<author>David L. Dill</author>
<title>Symbolic model checking for sequential circuit verification.</title>
<pages>401-424</pages>
<year>1994</year>
<volume>13</volume>
<journal>IEEE Trans. on CAD of Integrated Circuits and Systems</journal>
<number>4</number>
<ee>http://doi.ieeecomputersociety.org/10.1109/43.275352</ee>
<url>db/journals/tcad/tcad13.html#BurchCLMD94</url>
</article>
</dblp>
