A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations.

Sarvesh Bhardwaj Sarma B. K. Vrudhula Amit Goel A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. 1812-1825 2008 27 IEEE Trans. on CAD of Integrated Circuits and Systems 10 http://dx.doi.org/10.1109/TCAD.2008.927671 db/journals/tcad/tcad27.html#BhardwajVG08