@article{DBLP:journals/tcad/BhardwajVG08,
author = {Sarvesh Bhardwaj and
Sarma B. K. Vrudhula and
Amit Goel},
title = {A Unified Approach for Full Chip Statistical Timing and
Leakage Analysis of Nanoscale Circuits Considering Intradie
Process Variations},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {27},
number = {10},
year = {2008},
pages = {1812-1825},
ee = {http://dx.doi.org/10.1109/TCAD.2008.927671},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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