Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.

Mustafa Badaroglu Kris Tiri Geert Van der Plas Piet Wambacq Ingrid Verbauwhede Stéphane Donnay Georges G. E. Gielen Hugo De Man Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. 1146-1154 2006 25 IEEE Trans. on CAD of Integrated Circuits and Systems 6 http://doi.ieeecomputersociety.org/10.1109/TCAD.2005.855952 db/journals/tcad/tcad25.html#BadarogluTPWVDGM06