Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS.

Pramod V. Argade Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS. 33-40 1989 8 IEEE Trans. on CAD of Integrated Circuits and Systems 1 http://doi.ieeecomputersociety.org/10.1109/43.21816 db/journals/tcad/tcad8.html#Argade89