Filip Van Aelten Jonathan Allen Srinivas Devadas Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs. 122-134 1994 13 IEEE Trans. on CAD of Integrated Circuits and Systems 1 http://doi.ieeecomputersociety.org/10.1109/43.273743 db/journals/tcad/tcad13.html#AeltenAD94