Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.

Shobha Vasudevan Vinod Viswanath Robert W. Sumners Jacob A. Abraham Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. 1401-1414 2007 56 IEEE Trans. Computers 10 http://doi.ieeecomputersociety.org/10.1109/TC.2007.1073 db/journals/tc/tc56.html#VasudevanVSA07