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@article{DBLP:journals/tc/ParkDS04,
author = {Joonseok Park and
Pedro C. Diniz and
K. R. Shesha Shayee},
title = {Performance and Area Modeling of Complete FPGA Designs in
the Presence of Loop Transformations},
journal = {IEEE Trans. Computers},
volume = {53},
number = {11},
year = {2004},
pages = {1420-1435},
ee = {http://csdl.computer.org/comp/trans/tc/2004/11/t1420abs.htm},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2004-12-06 by Michael Ley (ley@uni-trier.de)