High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.

Shoji Kawahito Makoto Ishida Tetsuro Nakamura Michitaka Kameyama Tatsuo Higuchi High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. 34-42 1994 43 IEEE Trans. Computers 1 db/journals/tc/tc43.html#KawahitoINKH94