A Selective Trigger Scan Architecture for VLSI Testing.

Mohammad Hosseinabady Shervin Sharifi Fabrizio Lombardi Zainalabedin Navabi A Selective Trigger Scan Architecture for VLSI Testing. 316-328 2008 57 IEEE Trans. Computers 3 http://doi.ieeecomputersociety.org/10.1109/TC.2007.70806 db/journals/tc/tc57.html#HosseinabadySLN08