Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.

Ramaswamy Govindarajan Hongbo Yang José Nelson Amaral Chihong Zhang Guang R. Gao Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. 4-20 2003 52 IEEE Trans. Computers 1 http://computer.org/tc/tc2003/t0004abs.htm db/journals/tc/tc52.html#GovindarajanYAZG03