Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture.

David Morano Alireza Khalafi David R. Kaeli Augustus K. Uht Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture. 16-25 2003 31 SIGARCH Computer Architecture News 1 http://doi.acm.org/10.1145/773365.773368 db/journals/sigarch/sigarch31.html#MoranoKKU03