Stuck-at-fault testing for quasi-delay-insensitive logic circuits.

Arthit Thongtak Takashi Nanya Stuck-at-fault testing for quasi-delay-insensitive logic circuits. 19-27 1998 29 Systems and Computers in Japan 2 http://dx.doi.org/10.1002/(SICI)1520-684X(199802)29:2<19::AID-SCJ3>3.0.CO;2-T db/journals/scjapan/scjapan29.html#ThongtakN98