FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures.

Jiafeng Xie Jianjun He Guanzheng Tan FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. 365-370 2010 41 Microelectronics Journal 6 http://dx.doi.org/10.1016/j.mejo.2010.04.006 db/journals/mj/mj41.html#XieHT10