Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.

Xiaoyao Liang Ramon Canal Gu-Yeon Wei David Brooks Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability. 60-68 2008 28 IEEE Micro 1 http://doi.ieeecomputersociety.org/10.1109/MM.2008.12 db/journals/micro/micro28.html#LiangCWB08