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@article{DBLP:journals/micro/LiangCWB08,
author = {Xiaoyao Liang and
Ramon Canal and
Gu-Yeon Wei and
David Brooks},
title = {Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache
to Combat Process Variability},
journal = {IEEE Micro},
volume = {28},
number = {1},
year = {2008},
pages = {60-68},
ee = {http://doi.ieeecomputersociety.org/10.1109/MM.2008.12},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2008-06-05 by Michael Ley (ley@uni-trier.de)