Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.

Toru Asano Joel Silberman Sang H. Dhong Osamu Takahashi Michael White Scott R. Cottier Takaaki Nakazato Atsushi Kawasumi Hiroshi Yoshihara Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. 30-38 2005 25 IEEE Micro 5 http://doi.ieeecomputersociety.org/10.1109/MM.2005.94 db/journals/micro/micro25.html#AsanoSDTWCNKY05