1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing.

Tomonori Sekiguchi Kazuo Ono Akira Kotabe Yoshimitsu Yanagawa 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. 828-837 2011 46 J. Solid-State Circuits 4 http://dx.doi.org/10.1109/JSSC.2011.2109630 db/journals/jssc/jssc46.html#SekiguchiOKY11