BibTeX record journals/jssc/NosakaSIIKYSFYE04

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@article{DBLP:journals/jssc/NosakaSIIKYSFYE04,
  author       = {Hideyuki Nosaka and
                  Eiichi Sano and
                  Kiyoshi Ishii and
                  Minoru Ida and
                  Kenji Kurishima and
                  Shoji Yamahata and
                  Tsugumichi Shibata and
                  Hiroyuki Fukuyama and
                  Mikio Yoneyama and
                  Takatomo Enoki and
                  Masahiro Muraguchi},
  title        = {A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit
                  with a robust lock detector},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {39},
  number       = {8},
  pages        = {1361--1365},
  year         = {2004},
  url          = {https://doi.org/10.1109/JSSC.2004.831463},
  doi          = {10.1109/JSSC.2004.831463},
  timestamp    = {Sat, 30 Sep 2023 10:20:23 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/NosakaSIIKYSFYE04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}