BibTeX record journals/jssc/MakinoNSMSM96

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@article{DBLP:journals/jssc/MakinoNSMSM96,
  author       = {Hiroshi Makino and
                  Yasunobu Nakase and
                  Hiroaki Suzuki and
                  Hiroyuki Morinaka and
                  Hirofumi Shinohara and
                  Koichiro Mashiko},
  title        = {An 8.8-ns 54{\texttimes}54-bit multiplier with high speed redundant
                  binary architecture},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {31},
  number       = {6},
  pages        = {773--783},
  year         = {1996},
  url          = {https://doi.org/10.1109/4.509863},
  doi          = {10.1109/4.509863},
  timestamp    = {Tue, 26 Jul 2022 08:39:48 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/MakinoNSMSM96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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