BibTeX record journals/jssc/LiuSOSHDSPWWS19

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@article{DBLP:journals/jssc/LiuSOSHDSPWWS19,
  author       = {Hanli Liu and
                  Atsushi Shirane and
                  Kenichi Okada and
                  Zheng Sun and
                  Hongye Huang and
                  Wei Deng and
                  Teerachot Siriburanon and
                  Jian Pang and
                  Yun Wang and
                  Rui Wu and
                  Teruki Someya},
  title        = {A 265- {\textdollar}{\textbackslash}mu{\textdollar} {W} Fractional-
                  {\textdollar}\{N\}{\textdollar} Digital {PLL} With Seamless Automatic
                  Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked
                  Loop in 65-nm {CMOS}},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {12},
  pages        = {3478--3492},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2019.2936967},
  doi          = {10.1109/JSSC.2019.2936967},
  timestamp    = {Thu, 27 Jul 2023 08:18:19 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LiuSOSHDSPWWS19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}