BibTeX record journals/jssc/KishineFKI04

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@article{DBLP:journals/jssc/KishineFKI04,
  author       = {Keiji Kishine and
                  Kyoko Fujimoto and
                  Satomi Kusanagi and
                  Haruhiko Ichino},
  title        = {{PLL} design technique by a loop-trajectory analysis taking decision-circuit
                  phase margin into account for over-10-Gb/s clock and data recovery
                  circuits},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {39},
  number       = {5},
  pages        = {740--750},
  year         = {2004},
  url          = {https://doi.org/10.1109/JSSC.2004.826319},
  doi          = {10.1109/JSSC.2004.826319},
  timestamp    = {Fri, 22 Apr 2022 09:29:33 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/KishineFKI04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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