A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.

Yoshifumi Ikenaga Masahiro Nomura Shuji Suenaga Hideo Sonohara Yoshitaka Horikoshi Toshiyuki Saito Yukio Ohdaira Yoichiro Nishio Tomohiro Iwashita Miyuki Satou Koji Nishida Koichi Nose Koichiro Noguchi Yoshihiro Hayashi Masayuki Mizuno A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. 832-840 2012 47 J. Solid-State Circuits 4 http://dx.doi.org/10.1109/JSSC.2012.2185340 db/journals/jssc/jssc47.html#IkenagaNSSHSONISNNNHM12