<?xml version="1.0"?>
<dblp>
<article key="journals/jssc/DigheVAKJBHTEBDB11" mdate="2012-03-27">
<author>Saurabh Dighe</author>
<author>Sriram R. Vangal</author>
<author>Paolo A. Aseron</author>
<author>Shasi Kumar</author>
<author>Tiju Jacob</author>
<author>Keith A. Bowman</author>
<author>Jason Howard</author>
<author>James Tschanz</author>
<author>Vasantha Erraguntla</author>
<author>Nitin Borkar</author>
<author>Vivek K. De</author>
<author>Shekhar Borkar</author>
<title>Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.</title>
<pages>184-193</pages>
<year>2011</year>
<volume>46</volume>
<journal>J. Solid-State Circuits</journal>
<number>1</number>
<ee>http://dx.doi.org/10.1109/JSSC.2010.2080550</ee>
<url>db/journals/jssc/jssc46.html#DigheVAKJBHTEBDB11</url>
</article>
</dblp>
