Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.

Yen-Huei Chen Shao-Yu Chou Quincy Li Wei-Min Chan Dar Sun Hung-Jen Liao Ping Wang Meng-Fan Chang Hiroyuki Yamauchi Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. 969-980 2012 47 J. Solid-State Circuits 4 http://dx.doi.org/10.1109/JSSC.2012.2185180 db/journals/jssc/jssc47.html#ChenCLCSLWCY12