A parallel algorithm for constructing reduced visibility graph and its FPGA implementation.

K. Sridharan T. K. Priya A parallel algorithm for constructing reduced visibility graph and its FPGA implementation. 635-644 2004 50 Journal of Systems Architecture 10 http://dx.doi.org/10.1016/j.sysarc.2004.02.003 db/journals/jsa/jsa50.html#SridharanP04