Implications of VHDL timing models on simulation and software synthesis.

Venkatram Krishnaswamy Rajesh Gupta Prithviraj Banerjee Implications of VHDL timing models on simulation and software synthesis. 23-36 1997 44 Journal of Systems Architecture 1 http://dx.doi.org/10.1016/1383-7621(97)80001-X db/journals/jsa/jsa44.html#KrishnaswamyGB97