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@article{DBLP:journals/jsa/KrishnaswamyGB97,
author = {Venkatram Krishnaswamy and
Rajesh Gupta and
Prithviraj Banerjee},
title = {Implications of VHDL timing models on simulation and software
synthesis},
journal = {Journal of Systems Architecture},
volume = {44},
number = {1},
year = {1997},
pages = {23-36},
ee = {http://dx.doi.org/10.1016/1383-7621(97)80001-X},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
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