VHDL/S - integrating statecharts, timing diagrams, and VHDL.

Johannes Helbig Rainer Schlör Werner Damm Gert Döhmen Peter Kelb VHDL/S - integrating statecharts, timing diagrams, and VHDL. 571-580 1993 38 Microprocessing and Microprogramming 1-5 http://dx.doi.org/10.1016/0165-6074(93)90197-S db/journals/jsa/jsa38.html#HelbigSDDK93