A clocking technique for FPGA pipelined designs.

Oswaldo Cadenas Graham M. Megson A clocking technique for FPGA pipelined designs. 687-696 2004 50 Journal of Systems Architecture 11 http://dx.doi.org/10.1016/j.sysarc.2004.04.001 db/journals/jsa/jsa50.html#CadenasM04