Theodoros Antonakopoulos Nick Kanopoulos Multiple boundary scan-paths for minimizing circuit-board test-application time. 377-386 1994 40 Microprocessing and Microprogramming 6 http://dx.doi.org/10.1016/0165-6074(94)90104-X db/journals/jsa/jsa40.html#AntonakopoulosK94