Selective Clock-Gating for Low-Power Synchronous Counters.

Pilar Parra Antonio J. Acosta Raúl Jiménez Manuel Valencia Selective Clock-Gating for Low-Power Synchronous Counters. 11-19 2005 1 J. Low Power Electronics 1 http://dx.doi.org/10.1166/jolpe.2005.003 db/journals/jolpe/jolpe1.html#ParraAJV05