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@article{DBLP:journals/integration/ZhangS08,
author = {Tianpei Zhang and
Sachin S. Sapatnekar},
title = {Buffering global interconnects in structured ASIC design},
journal = {Integration},
volume = {41},
number = {2},
year = {2008},
pages = {171-182},
ee = {http://dx.doi.org/10.1016/j.vlsi.2007.04.002},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2008-06-25 by Michael Ley (ley@uni-trier.de)