BibTeX record journals/integration/SinghJMYSJG18

download as .bib file

@article{DBLP:journals/integration/SinghJMYSJG18,
  author       = {Kunwar Singh and
                  Aman Jain and
                  Aviral Mittal and
                  Vinay Yadav and
                  Atul Anshuman Singh and
                  Anmoll Kumar Jain and
                  Maneesha Gupta},
  title        = {Optimum transistor sizing of {CMOS} logic circuits using logical effort
                  theory and evolutionary algorithms},
  journal      = {Integr.},
  volume       = {60},
  pages        = {25--38},
  year         = {2018},
  url          = {https://doi.org/10.1016/j.vlsi.2017.08.003},
  doi          = {10.1016/J.VLSI.2017.08.003},
  timestamp    = {Tue, 07 May 2024 20:27:07 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/SinghJMYSJG18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.