BibTeX record journals/integration/QinWMMH20

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@article{DBLP:journals/integration/QinWMMH20,
  author       = {Maoyuan Qin and
                  Xinmu Wang and
                  Baolei Mao and
                  Dejun Mu and
                  Wei Hu},
  title        = {A formal model for proving hardware timing properties and identifying
                  timing channels},
  journal      = {Integr.},
  volume       = {72},
  pages        = {123--133},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.02.001},
  doi          = {10.1016/J.VLSI.2020.02.001},
  timestamp    = {Tue, 24 Mar 2020 10:08:28 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/QinWMMH20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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