A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.

Jong-Ru Guo Chao You Kuan Zhou Michael Chu Peter F. Curran Jiedong Diao Bryan S. Goda Russell P. Kraft John F. McDonald A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. 525-540 2005 38 Integration 3 http://dx.doi.org/10.1016/j.vlsi.2004.07.005 db/journals/integration/integration38.html#GuoYZCCDGKM05