<?xml version="1.0"?>
<dblp>
<article key="journals/integration/DiYD06" mdate="2007-06-18">
<author>Jia Di</author>
<author>Jiann S. Yuan</author>
<author>Ronald F. DeMara</author>
<title>Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.</title>
<pages>90-112</pages>
<year>2006</year>
<volume>39</volume>
<journal>Integration</journal>
<number>2</number>
<ee>http://dx.doi.org/10.1016/j.vlsi.2004.08.002</ee>
<url>db/journals/integration/integration39.html#DiYD06</url>
</article>
</dblp>
