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@article{DBLP:journals/integration/DiYD06,
author = {Jia Di and
Jiann S. Yuan and
Ronald F. DeMara},
title = {Improving power-awareness of pipelined array multipliers
using two-dimensional pipeline gating and its application
on FIR design},
journal = {Integration},
volume = {39},
number = {2},
year = {2006},
pages = {90-112},
ee = {http://dx.doi.org/10.1016/j.vlsi.2004.08.002},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2007-06-18 by Michael Ley (ley@uni-trier.de)