A system-level framework for designing and evaluating protocol processor architectures.

Seppo Virtanen Tero Nurmi Jani Paakkulainen Johan Lilius A system-level framework for designing and evaluating protocol processor architectures. 78-90 2005 1 IJES 1/2 http://dx.doi.org/10.1504/IJES.2005.008810 db/journals/ijes/ijes1.html#VirtanenNPL05