Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high-speed switch/router.

Ling Wu Cheng Li Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high-speed switch/router. 159-186 2009 22 Int. J. Communication Systems 2 http://dx.doi.org/10.1002/dac.966 db/journals/ijcomsys/ijcomsys22.html#WuL09