A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses.

Hiroyuki Yamauchi Toshikazu Suzuki Yoshinobu Yamagami A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. 749-757 2007 90-C IEICE Transactions 4 http://dx.doi.org/10.1093/ietele/e90-c.4.749 db/journals/ieicet/ieicet90c.html#YamauchiSY07