Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.

Tetsuya Yamada Masahide Abe Yusuke Nitta Kenji Ogura Manabu Kusaoke Makoto Ishikawa Motokazu Ozawa Kiwamu Takada Fumio Arakawa Osamu Nishii Toshihiro Hattori Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. 287-294 2006 89-C IEICE Transactions 3 http://dx.doi.org/10.1093/ietele/e89-c.3.287 db/journals/ieicet/ieicet89c.html#YamadaANOKIOTANH06